In recent years, in a semiconductor integrated circuit in which a high withstand voltage element and a low withstand voltage element are formed on a main surface of an SOI substrate, a dielectric isolation method that combines an SOI substrate and a trench isolation has been used. This dielectric isolation method can shorten an insulation isolation distance between the elements as compared with a junction isolation method, and therefore, it has the advantage of being able to enhance the integration degree of the semiconductor integrated circuit. Moreover, this dielectric isolation method can remove parasitic transistors between the elements in principle, and as a result, malfunction such as latch-up or the like can be prevented and reliability of the semiconductor integrated circuit can be improved.
For example, Japanese Patent No. 3189456 (Patent Document 1) discloses an SOI semiconductor device using a dielectric isolation substrate. In this SOI semiconductor device, an isolation trench is formed to reach a semiconductor supporting substrate through a silicon oxide film from a front surface side of a semiconductor layer, and a polycrystalline semiconductor layer filled in the isolation trench is conductively connected to the semiconductor substrate. Also, to a rear surface of the semiconductor supporting substrate, a filling-layer-potential specifying electrode for applying a predetermined potential to the polycrystalline semiconductor layer through the semiconductor supporting substrate is conductively connected.